Charge pump level converter (CPLC) for dual voltage system in very low power application

ABSTRACT

Recent efforts are underway to develop LSI circuits that operate at power supply voltages of 1-V or lower. It is a desire that this low core voltage circuits interface to 3.3-V I/O supply. A charge pump level converter for dual power supply application is proposed using low power and high speed interface to higher I/O supply. This circuit does not consume DC power it is suitable for low power and high speed interface and can be implemented using complementary metal-oxide-semiconductor (CMOS) fabrication processes.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to CMOS (complementary metal-oxide semiconductor) Integrated circuits (IC's) and more specifically to a charge pump level converter (CPLC) for translating low core 1-V to high-speed 3.3-V I/O interface.

[0003] 2. Description of Related Art

[0004] Advances in CMOS technology are driving the operating core voltage of IC's lower. As device dimensions shrink, the voltage of the core logic, scales down proportionally in order to avoid gate-oxide breakdown and hot electron effects.

[0005] However, the 3.3-V I/O interface remains constant.

[0006] Complex integrated circuits operating with supply voltages of 1-V or lower have been demonstrated. In order to incorporate these circuits into existing systems it is necessary to provide interfaces from the low voltage logic to logic devices operating at 3.3-V or higher.

[0007] The often seen level converter is DCVS (Differential Cascode Voltage Switch) shown in FIG. 1. The DCVS shown in FIG. 1 becomes too slow or fails, and is unacceptable because the core voltage approaches or is even lower than the threshold voltage Vt of the thick oxide device of the 3.3-V MOSFET.

[0008] The low voltage NMOS's (MN11, MN21) are exposed to the I/O high drain voltage that can give electrons sufficient energy that they are injected into the gate oxide and cause permanent damage also known as hot electron effect.

[0009] In order to protect the 1.0-V NMOS transistors (MN12, MN22) from high drain voltage stress, a zero-Vt 3.3-V NMOS (MN11, MN21) transistors are used to isolate the output node voltages OUT and {overscore (OUT)} from transistors MP11 and MP21 as shown in FIG. 2.

[0010] This approach is utilizing a large layout area, it is too slow due to the large zero-Vt NMOS device which has large parasitic capacitive loading on the output node, and the fabrication process must provide for native device which is not readily available in conventional CMOS fabrication process.

[0011] Related art on the subject of level-up converters circuits has been presented in the literature by:

[0012] Y. Kanno, et al, “Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs,” in Proc. of Symp. On VLSI Circuit, June 2000, pp. 202-203.

[0013] Wen-Tai Wang, Level shifters for high-speed 1-V to 3.3-V interfaces in a 0.13 um Cu-interconnection/low-k CMOS technology,” in VLSI Technology, Systems and Applications, 2001. Proc. Of Technical Papers, 2001 International Symposium, 2001 pp 301-307.,

[0014] Kan M. Chu and David I. Pulfrey, “Design Procedures for Differential Cascode Voltage Switch Circuits”, EEE journal of Solid State Circuits Vol SC-21, No 6, pp 1082-1087 pp 1-82-1087, December 1986.

[0015] U.S. Pat. No. 6,356,137 Voltage boost circuit with low power supply voltage by Farzan Roohparvar

[0016] K. Joe Hass, David F. Cox: Level Shifting Interfaces for Low Voltage Logic, 9^(th) NASA Symposium on VLSI Design 2000

[0017] Seong-Ook Jung, Ki-Wook Kim Sung-Mo Kang: “Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltages”

[0018] However none of the above related art achieve high speed from 1-V to 3.3-V I/O interface, use only basic CMOS devices and result in smaller layout area.

SUMMARY OF THE INVENTION

[0019] It is an object of one embodiment of the present invention to speed up the level conversion from low core 1-V to a 3.3-V I/O interface through the use of a charge pump level converter.

[0020] It is another object of the present invention to use basic CMOS devices only, and to minimize layout area.

[0021] These objects are achieved by voltage multiplication of the input signal swing using diode connected NMOS transistor with self-nwell PMOS transistor serving as a capacitor thus providing a better charge pump efficiency.

[0022] A better understanding of the nature and advantages of the charge pump level converter circuit according to the present invention will be gained with reference to the detailed description below and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a circuit schematic of a prior art Differential Cascode Voltage Switch;

[0024]FIG. 2 is a circuit schematic of a prior art Zero-Vt Level Shifter;

[0025]FIG. 3 is an exemplary circuit implementation, for the charge pump level converter according to a specific embodiment of the present invention;

[0026]FIG. 4 shows the simulation result and comparison between DCVS, Zero-Vt and CPLC circuit configurations.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0027]FIG. 3 shows the topology for the level shift charge pump level converter (CPLC) according to the present invention.

[0028] The CPLC is comprised of two inputs and two outputs. IN is the inphase or true input, and {overscore (IN)} is the out-of-phase or complement input. The outputs are: OUT which is the inphase or true output, and {overscore (OUT)} which is the out-of-phase or complement output. The circuit operates between ground and VDDH, which is the higher I/O voltage, and ground and VDDL which is the lower core voltage supply.

[0029] The operation of the circuit is as follows:

[0030] with the in-phase input IN at logical “0” (ground) and the out-of-phase input {overscore (IN)} at logical “1” (VDDL), node N1 is pre-charged to (VDDL-Vtn) through the diode connected NMOS device MN13; when the out-of phase input {overscore (IN)} is at logical “0” and the in-phase input IN is at logical “1”, node N2 is pre-charged to (VDDL-Vtn) through the diode connected NMOS device MN23.

[0031] Vtn is the threshold of NMOS devices MN13 & MN23. MN13 & MN23 are thin oxide devices.

[0032] When the inphase input IN switches from a logic “0” to a logic “1” (0 to VDDL) and the out-of-phase input {overscore (IN)} switches from a logic “1” to a logic “0” (VDDL to 0), the voltage at node N1 is boosted to (VDDL-Vtn)+VDDL=(2VDDL-Vtn) through the coupling that takes place via self-nwell PMOS transistor MP 12 that acts as a capacitor.

[0033] The PMOS self-nwell MP12 does not have a leakage path so it is more efficient than an NMOS capacitor which normally has a leakage path to substrate and gets worse performance. The capacitor formed by PMOS self-nwell configuration is as close as possible to an ideal case.

[0034] By separating the N well of MP12 & MP22 from other PMOS's (MP11 & MP21) makes charge pumping more efficient.

[0035] The coupling capacitance provided by the use of the self-nwell PMOS configuration provides a larger gate drive (Vgs) in order to turn on NMOS device MN11.

[0036] MN11 & MN21 are thick oxide devices and have larger Vt.

[0037] As a result of IN transitioning from logic “0” to “1” and {overscore (IN)} from “1” to “0” the out-of-phase output {overscore (OUT)} discharges to logic “0”, MN22 turns off and MP21 turns on driving in-phase node OUT to logic “1” (VDDH). Turning off MN21 when MP21 pulls up isolates the parasitic capacitance C1 from node OUT and thus results in increased switching speed.

[0038] When {overscore (IN)} transitions from “0” to “1” and IN from “1” to “0” the in-phase output OUT discharges to logic “0”, MN12 turns off and MP11 turns on driving out-of-phase node {overscore (OUT)} to logic “1” (VDDH). Turning off MN11 when MP11 pulls up isolates the parasitic capacitance C2 from node {overscore (OUT)}.

[0039] Thick oxide MN11 & MN21 form a cascode structure in order to bias and protect the thin oxide NMOS MN12 & MN22 against VDDH over-stress.

[0040] Lower core voltage at IN could be converted to higher I/O voltage at OUT even if core voltage VDDL is lower than the threshold voltage (Vt) of thick oxide device.

[0041] In summary the present invention of CPLC speeds up the conversion speed from very low core voltage to higher I/O voltage. It uses basic complementary devices only, and occupies smaller layout area.

[0042] While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A complementary metal oxide-semiconductor(CMOS) charge pump level converter circuit having a low core differential input signal that is converted to a high differential output voltage, the charge pump level converter comprising: a first charge pump level converter circuit used to generate an elevated output signal in response to the input signal; a second charge pump level converter circuit used to generate an elevated output signal in response to an input signal of the same amplitude as the said first input signal but inverted with respect to the first said input signal; a differential cascode voltage switch circuit whose inputs are coupled to said first and second voltage elevated output signals in order to generate a high differential output voltage, wherein the first and second elevated output signals comprises: a first precharge transistor coupled between a first power supply and said first precharge node and having an input coupled to said first power supply; a second precharge transistor coupled between a first power supply and said second precharge node and having an input coupled to said first power supply; a first charge transfer transistor serving as a capacitor having a first terminal coupled to the first precharge node and a second terminal coupled to the first input signal; and a second charge transfer transistor serving as a capacitor having a first terminal coupled to the second precharge node and a second terminal coupled to the second input signal.
 2. The charge pump level converter circuit of claim 1, wherein the first precharge transistor is a diode connected NMOS transistor.
 3. The charge pump level converter circuit of claim 1, wherein the first charge transfer transistor is a P-channel transistor whose drain and source are tied to said P-channel transistor's body terminal.
 4. The charge pump level converter circuit of claim 1, wherein the second charge transfer transistor is a P-channel transistor whose drain and source are tied to said P-channel transisor's body terminal.
 5. The charge pump level converter circuit of claim 3, wherein the body terminal of the charge transfer transistor couples to said first precharge node.
 6. The charge pump level converter circuit of claim 4, wherein the body terminal of the charge transfer transistor couples to said second precharge node.
 7. The charge pump level converter circuit of claim 3, wherein the gate control terminal of said first charge transfer transistor couples to the first input signal.
 8. The charge pump level converter circuit of claim 4, wherein the gate control terminal of said second charge transfer transistor couples to the second input signal.
 9. The charge pump level converter circuit of claim 1, wherein the charge pump boosts the voltage level of the input signal to a voltage level at least twice the voltage level of the input signal.
 10. The charge pump level converter circuit of claim 1, wherein the power supply provides a positive supply voltage, and the low potential is ground.
 11. The charge pump level converter of claim 1, wherein the DCVS circuit comprises: a push-pull load; and a pair of DCVS binary tree.
 12. The charge pump level converter of claim 11, wherein the push-pull load is a cross-coupled P-channel transistors.
 13. The charge pump level converter of claim 12, wherein the control gate signal on the P-channel transistor on the right hand side is the complement output node {overscore (OUT)}, of the one on the left hand side node OUT.
 14. The charge pump level converter of claim 11, wherein the left side leg of the DCVS tree is a pair of two N-channel transistors in series.
 15. The charge pump level converter of claim 14, wherein one terminal of the two N-channel transistors is coupled to the complement node output {overscore (OUT)}, and the second terminal of the bottom N-channel transistor is coupled to ground.
 16. The charge pump level converter of claim 14, wherein one gate control of the bottom N-channel transistor is coupled to the first input signal IN, and the second gate control of the top N-channel transistor is coupled to the first precharge node N1.
 17. The charge pump level converter of claim 11, wherein the right side leg of the DCVS tree is a pair of two N-channel transistors in series.
 18. The charge pump level converter of claim 17, wherein one terminal of the two N-channel transistors is coupled to the complement node output {overscore (OUT)}, and the second terminal of the bottom N-channel transistor is coupled to ground.
 19. The charge pump level converter of claim 17, wherein one gate control of the bottom N-channel transistor is coupled to the first input signal IN, and the second gate control of the top N-channel transistor is coupled to the said second precharge node N2.
 20. The charge pump level converter of claim 11, wherein the second power supply provides a positive supply voltage and the low potential is ground.
 21. A method of converting a low swing differential input voltage to a high-speed I/O differential interface, comprising: elevating a first input signal using a first charge pump converter circuit to generate a first elevated signal; elevating a second input signal using a second charge pump converter circuit to generate an elevated signal in response to an input signal of the same amplitude as the first input signal but inverted with respect to the first said input signal; and a differential cascode voltage switch circuit whose inputs are coupled to said first and second elevated output signals in order to generate a high differential output voltage.
 22. The method of claim 21 wherein one charge pump converter is comprised of a N-channel transistor whose gate and drain are tied to a first power supply and body tied to ground, thus serving as a resistor, and a P-channel transistor whose drain, source and body are tied together to form a capacitor and connected to the source of said N-channel transistor, while the gate of the P-channel transistor is connected to first input terminal.
 23. The method of claim 21 wherein a second charge pump converter is comprised of a second N-channel transistor whose gate and drain are tied to same first power supply and body tied to ground, thus serving as a resistor, and a P-channel transistor whose drain, source and body are tied together to form a capacitor and connected to the source of said N-channel transistor, while the gate of the P-channel transistor is connected to second input terminal.
 24. The method of claim 21 wherein a differential cascode voltage switch is comprised of a cross-coupled P-channel push-pull transistor load and a pair of Differential Cascode Voltage Switch binary tree (DCVS).
 25. The method of claim 24 wherein the cross-coupled P-channel transistors have the body and source tied to a second power supply, with the gate of one P-channel transistor on the right side connected to the (out-of-phase) output node and the gate of the second P-channel transistor on the left side connected to the (in-phase) output node.
 26. The method of claim 24 wherein said DCVS is comprised of two pairs of two N-channel transistor in series, one terminal of the first pair is coupled to the complement node output, and the second terminal of the bottom N-channel transistor (of the first pair) is coupled to round; the other terminal of the second pair is coupled to the true node output, with the second terminal of the bottom N-channel transistor (of the second pair) coupled to ground; one gate input of the left side bottom N-channel transistor is coupled to the inphase input signal while the second gate of the top N-channel transistor is coupled to first internal precharge node; the second input on the right side bottom N-channel transistor is coupled to the out-of-phase (complement) input signal while the second gate of the top N-channel transistor is coupled to the second internal precharge node. 